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EDA-Tools: Verilog Gate-Level Studio for hardware engineers.
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EDA-Tools is​ a user-friendly HW engineering studio comprising of an array of tools specially designed for performing reports and manipulation on Verilog gate-level netlists.
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EDA-Tools assume a valid Verilog gate-level file as input, Bus notation is not supported.
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The current release of EDA-Tools is a 'generic' engineering tool – it operates without the need of loading a vendor library of cells.
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EDA-Tools is designed to operate as a quick prototyping tool (before the sign-off tool). You can perform the manipulations and reports on 'semi-finished' designs and defer the decision on the technology and vendor - the tools are smart enough to differentiate between instances of modules and library gates without a loaded library.
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Currently the following tools are available (NOTE: Bus notation is currently not supported):
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Manipulations - Replace library gates, Remove buffers, Uppercase ports.
Reports - Count library gates, List physical paths, List library gates
Feature requests
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​We're always excited to hear your ideas. Here are a few things people have asked us to add to EDA-Tools.
Email your vote for any you'd like to see
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Selective Flattening Tools:
a. Flatten modules by number of library gates.
b. Flatten modules of conversion library.
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Reduction Tools:
a. Reduce gates with tied inputs.
b. Remove instances of library gates with open outputs.
c. Reduce chains of one-input gates.
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Netlist Editing Tools:
a. Propagate global-reset from a defined module till the top of the design.
b. Propagate a specific output port from a defined module till the top of the design.
Reporting Tools:
a. Fan-out Report.
b. Floating / Multi-driven Inputs Report.
c. Gated Clock Report.
d. Long Data-Paths Report.
Additional Tools:
a. Bus opener tool.
b. Preliminary power and size estimation tool.
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Have another new idea for EDA-Tools?
Share your idea with us here